1. Field of the Invention
The invention generally relates to an electronic memory device.
2. Description of the Relevant Art
Ongoing technological progress has resulted in the integration of more and more complex systems on a semiconductor chip, the systems comprising a number of functional modules.
The memory requirements of such systems integrated on a chip have increasingly developed in parallel. This development has promoted the use of large capacity memories known as DRAM.
To satisfy these increasing needs, so called embedded DRAM memories were initially developed by combining DRAM memory technologies with logic process technologies.
However, for reasons of cost and design, for the most part, embedded DRAM memories have had to be abandoned in favor of DRAM on dedicated chips.
DRAM memories of this kind separate from the system chip are accessible via low level physical interfaces, for example of the DDR type, for the most common ones, or of the Rambus® type for higher performance ones.
The increased need for large capacity memories has therefore resulted in an increased number of communication interfaces with DRAMs on the system chip and a constant increase in the bit rates of information exchange with the outside.
The solutions adopted for current DRAM interfaces have a certain number of drawbacks.
First of all, these are low level interfaces, i.e. they carry the elementary commands of the DRAM and their sequencing in the form of signals or signal packets, while conforming to the inter-command distances specified by the DRAM designers, to the nearest cycle.
Moreover, for the most common interfaces, the number of signals to be carried is fairly high and increasing, currently from 48 to 160 signals, and they generally use a mesochronous link, which makes them difficult to produce.
Furthermore, in order to limit the number of signals at the DRAM interfaces, two-way buses are used. However, the turnaround time of the bus then affects the performance of the interface, and a memory controller has to organize access so as to minimize the number of turnarounds of the bus.
To summarize, the DRAM interfaces are currently one of the major limiting factors for the performance of the system.